1. Technical Field
This disclosure relates to driver circuits.
2. Description of the Related Art
The following descriptions and examples are given as background only.
The transmission of data involves sending and receiving data over a transmission path, which is connected between a pair of transceivers. Each transceiver may include a receiver and a transmitter (or output driver). The receiver functions to receive data from the transmission path, while the transmitter functions to drive data onto the transmission path. The transfer of data between receiver and transmitter circuits fabricated on separate chips is sometimes referred to as “off-chip” signaling or “chip-to-chip” communication.
Single-ended signals are typically used for on-chip communication because of the reduced area consumption and design complexity generally involved in routing these signals. However, more and more off-chip signals, or signals used for chip-to-chip communication, are routed as differential signals because of their decreased sensitivity to environmental noise. For this reason, numerous interface standards such as Low Voltage Differential Signaling (LVDS), Stub Series Terminated Logic (SSTL), differential High-Speed Transceiver Logic (HSTL) and Low Voltage Positive Referenced Emitter Coupled Logic (LVPECL) have been established for sending and receiving differential signals across a transmission path. The differential signals used by these standards typically have smaller amplitudes (i.e., reduced swings) to facilitate high speed chip-to-chip communications.
LVDS, in particular, is a low swing, differential signaling technology with relatively high data transmission rates (ranging, e.g., from 100's of Mbps to more than 2 Gbps). In addition to high-speed, LVDS driver circuits provide low noise and low power consumption across a wide range of operating frequencies. These advantages have made LVDS a very popular data transmission standard. For example, LVDS is currently used in a broad range of applications, including various computing applications (e.g., flat panel displays, SCI processor interconnects and multimedia links), telecommunication and data communication applications (e.g., switches, hubs, routers, access systems and base stations) and consumer applications (e.g., home video links and set top boxes).
A typical LVDS driver is shown in FIG. 5. In the illustrated embodiment, the LVDS driver (150) is implemented with two pairs of complementary transistors (P1/N1 and P2/N2) coupled between a power supply and ground. A current source (CS) is coupled for driving the differential lines with a nominal drive current (e.g., 3.5 mA). As shown in FIGS. 1 and 5, the differential output signals (OUT, OUTB) generated between the complementary transistors may be driven across a transmission path 40 to a receiver 50. Most receivers are designed with high DC input impedance, so that a majority of the drive current flows across a small termination resistor (e.g., a 100Ω resistor) connected between the receiver inputs. When the driver circuit switches, the direction of current flow across the resistor changes to generate a logic high or logic low signal at the input of the receiver.
In some cases, a feedback amplifier 160 may be included to regulate the common mode voltage (vcm) of the differential output signals generated by the driver circuit. If included, the feedback amplifier may compare the common mode voltage to a reference voltage (vref) of about 1.25 volts. The voltage difference between the common mode and reference voltages may then be supplied back to the current source (CS) for adjusting the drive current. In this manner, the feedback control mechanism may be used to maintain the common mode voltage within an acceptable range.
Although LVDS circuits provide many advantages, conventional driver circuits tend to be very sensitive to circuit load conditions. For example, off-chip loads may drive the output pins of driver circuit 150 when the driver is disabled (i.e., when transistors P1, N1, P2 and N2 are inactive), causing the common mode voltage level to drift somewhere between the power supply and ground. The voltage drift is unknown and could be significant. When the driver circuit is subsequently re-enabled, the feedback amplifier may need a lot of time to stabilize the common mode voltage level and restore its output level. The time needed for the feedback amplifier to perform these functions is generally referred to as the “output enable time.” Lengthy output enable times cause problems within systems employing the driver circuit by delaying the driver output signal. A need, therefore, exists for an improved LVDS driver circuit and method for improving the output enable timing of an LVDS driver circuit.